Intel has officially released its next-generation desktop Core processor and its 500 series motherboard, continuing its battle with AMD. Although there is a complete renovation of the architecture and technology, it is still a 14nm process, with only eight cores and 16 threads at most.
Today's release of the Rocket Lake kernel gives us a glimpse of how it differs from previous architectures, especially Tiger Lake, which is also part of the 11th generation but is designed to be thin and light.
The architecture for the Rocket Lake CPU part, codenamed Cypress Cove, is said to be the result of the (unconfirmed) re-tuning of the Willow Cove architecture in Tiger Lake for the 14nm process, which is quite different.
Level 1 data caches and level 1 instruction caches are the same for each core.
The level 2 cache Willow Cove has 1.25MB per core, with up to four centers totaling 5MB, Cypress Cove has 512KB per core, and up to eight seats totaling 4MB, which is still double the 256KB per core Skylake has used for many years.
The Level 3 cache Willow Cove is a 3MB block per core, the QuadCore is 12MB, Cypress Cove is a 2MB block per seat, and the Eight-Core is 16MB. Of course, each of these cores has access to all three cache capacity levels.
In terms of GPU kernel display, both are new XE LP microarchitectures, and both are the 12.1 generation.
However, Tiger Lake integrates up to 96 execution cells (768 cores), with a level 3 cache capacity of 3.84MB. Rocket Lake has 32 cells (256 seats), with a level 3 cache capacity halved to 1.92MB.
Tiger Lake supports LPDDR4-4266, LPDDR5-5400MHz, and DDR4-3200MHz memory with 4 PCIe 4.0 channels, while Rocket Lake only supports DDR4-3200 memory with 20 PCIe 4.0 channels, which is the same as one graphics card and one SSD.
Also, Tiger Lake has an IPU V6 unit for AI acceleration, and the Thunderbolt 4 controller offers four interfaces, none of which Rocket Lake lacks.
Data on Rocket Lake's core area and transistors are not yet available, and Intel has long been silent on these metrics.
